Listar Ponencias (Arquitectura y Tecnología de Computadores) por agencia financiadora 

Listar Ponencias (Arquitectura y Tecnología de Computadores) por agencia financiadora "Ministerio de Ciencia y Tecnología (MCYT). España"

Mostrando ítems 1-5 de 5

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      A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion 

      Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé; Velarde Ramírez, Jesús (IEEE Computer Society, 2004)
      A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a ...
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      eDiab: A System for Monitoring, Assisting and Educating People with Diabetes 

      Fernández Luque, Luis; Sevillano Ramos, José Luis; Hurtado Núñez, F.J.; Moriana García, F.J.; Díaz del Río, Fernando; Cascado Caballero, Daniel (Springer, 2006)
      In this paper, a system developed for monitoring, assisting and educating people with diabetes, named eDiab, is described. ...
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      Inter-spike-intervals Analysis of Poisson Like Hardware Synthetic AER Generation 

      Linares Barranco, Alejandro; Oster, Matthias; Cascado Caballero, Daniel; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Linares Barranco, Bernabé (Springer, 2005)
      Address-Event-Representation (AER) is a communication protocol for transferring images between chips, originally developed ...
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      Performance analysis of single-slave Bluetooth piconets under cochannel interference 

      Cascado Caballero, Daniel; Sevillano Ramos, José Luis; Vicente Díaz, Saturnino; Díaz del Río, Fernando; Jiménez Moreno, Gabriel; Linares Barranco, Alejandro; Civit Balcells, Antón (IEEE Computer Society, 2004)
      We present an analytical model for single-slave Bluetooth piconets when the coexistence of multiple interfering devices ...
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      Poisson AER generator: Inter-Spike-Intervals Analysis 

      Linares Barranco, Alejandro; Cascado Caballero, Daniel; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Oster, Matthias; Linares Barranco, Bernabé (IEEE Computer Society, 2006)
      Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, ...