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Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are ...
Artículo
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
(Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...