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Author
Avedillo de Juan, María José (6)
Nuñez Martínez, Juan (6)Subject
Steep subthreshold slope (6)
Tunnel transistors (6)
Low supply voltage (5)Low power (4)Energy efficieny (3)Energy efficiency (1)Energy harvesting (1)Fine-grained pipeline (1)Noise coupling (1)Optimal design points (1)... View MoreDate Issued2017 (4)2016 (2)Funding agencyMinisterio de Economía y Competitividad (MINECO). España (5)Has file(s)Yes (6)

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Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs [Article]

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
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Assessing application areas for tunnel transistor technologies [Presentation]

Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
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Complementary tunnel gate topology to reduce crosstalk effects [Presentation]

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers (IEEE), 2017)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges ...
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Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas [Article]

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016)
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than ...
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Exploring logic architectures suitable for TFETs devices [Presentation]

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are ...
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Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications [Article]

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this ...
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