• Ponencia
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      Gate-Level Simulation of CMOS Circuits Using the IDDM Model 

      Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)
      Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ...
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      HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model 

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)
      This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ...