Now showing items 1-20 of 24

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      A practical floating-gate Muller-C element using vMOS threshold gates  [Article]

      Rodríguez Villegas, Esther; Huertas Sánchez, Gloria; Avedillo de Juan, María José; Quintana Toledo, José María; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 2001)
      This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates ...
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      Una aproximación al diseño óptimo de máquinas de estados finitos  [PhD Thesis]

      Avedillo de Juan, María José (1992-01-01)
      En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del número de estados en máquinas incompletamente especificadas, recogemos el estado del arte del problema, ...
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      Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits  [Presentation]

      Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03)
      The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor ...
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      COPAS: A New Algorithm for the Partial Input Encoding Problem  [Article]

      Martínez, Manuel; Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Hindawi Publishing Corporation, 2002)
      Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols should be chosen to optimize the final implementation. Conventionally, this input encoding (IE) problem ...
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      Diseño lógico de circuitos digitales usando dispositivos con característica NDR  [PhD Thesis]

      Núñez Martínez, Juan (2011-02-04)
      En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos con una, o varias, regiones de resistencia diferencial negativa (Negative Differential Resistance, ...
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      Domino inspired MOBILE networks  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)
      MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported ...
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      Efficient realization of a threshold voter for self-purging redundancy  [Article]

      Quintana Toledo, José María; Avedillo de Juan, María José; Huertas Díaz, José Luis (Springer, 2001)
      The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, the threshold voter. A very efficient implementation of this voter is presented which uses a ...
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      Efficient state reduction methods for PLA-based sequential circuits  [Article]

      Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1992)
      Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are ...
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      Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014)
      Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without ...
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      GELSA: un colocador flexible para circuitos integrados analógicos  [PhD Thesis]

      Prieto Rodríguez, Juan Antonio (2001-07-23)
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      Holding Dissapearance in RTD-based Quantizers  [Presentation]

      Nuñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Laboratoire TIMA, 2007)
      Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. The operation ...
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      Improved nanopipelined RTD adder using generalized threshold gates  [Article]

      Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011)
      Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these ...
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      Nu MOS-based sorter for arithmetic applications  [Article]

      Rueda Rueda, Adoración; Rodríguez Villegas, Esther; Quintana Toledo, José María; Avedillo de Juan, María José; Huertas Sánchez, Gloria (2000)
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      Redes MOBILE MOS-NDR operando con reloj de una fase  [Presentation]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (2010)
      La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative Differential Resistance, NDR) resulta atractiva desde el punto de vista del diseño de circuitos, como ...
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      RTD based logic circuits using generalized threshold gates  [Presentation]

      Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (2008)
      Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these ...
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      RTD-CMOS pipelined networks for reduced power consumption  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011)
      The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. ...
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      Simplified single-phase clock scheme for MOBILE networks  [Article]

      Núñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2011)
      MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required for this. A single-phase scheme is possible adding ...
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      Sorting networks implemented as νMOS circuits  [Article]

      Rodríguez Villegas, Esther; Quintana Toledo, José María; Avedillo de Juan, María José; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 1998)
      A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.
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      State merging and state splitting via state assignment: a new FSM synthesis algorithm  [Article]

      Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1994)
      The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and eventually, incompletely specified codes. In this new approach, state-reduction and state assignment ...