Now showing items 1-17 of 17

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      Assessing application areas for tunnel transistor technologies  [Presentation]

      Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
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      Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016)
      In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than ...
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      Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
      Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
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      Complementary tunnel gate topology to reduce crosstalk effects  [Presentation]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges ...
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      Design methodology for low-jitter differential clock recovery circuits in high performance ADCs  [Article]

      Nuñez Martínez, Juan; Ginés Arteaga, Antonio José; Peralías Macías, Eduardo; Rueda Rueda, Adoración (Springer, 2016)
      This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design ...
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      DOE based high-performance gate-level pipelines  [Presentation]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintero Álvarez, Héctor Javier (Institute of Electrical and Electronics Engineers, 2014)
      Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the noninverting behavior of domino gates, there ...
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      Domino inspired MOBILE networks  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)
      MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported ...
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      Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014)
      Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without ...
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      Exploring logic architectures suitable for TFETs devices  [Presentation]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
      Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are ...
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      Holding Dissapearance in RTD-based Quantizers  [Presentation]

      Nuñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Laboratoire TIMA, 2007)
      Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. The operation ...
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      Improving robustness of dynamic logic based pipelines  [Presentation]

      Quintero Álvarez, Héctor Javier; Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2016)
      Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the noninverting behavior of Domino gates, there ...
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      Improving speed of tunnel FETs logic circuits  [Article]

      Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2015)
      Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit ...
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      Insights Into the Operation of Hyper-FET-Based Circuits  [Article]

      Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2017)
      Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This ...
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      Redes MOBILE MOS-NDR operando con reloj de una fase  [Presentation]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (2010)
      La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative Differential Resistance, NDR) resulta atractiva desde el punto de vista del diseño de circuitos, como ...
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      Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)
      RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this ...
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      RTD-CMOS pipelined networks for reduced power consumption  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011)
      The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. ...
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      Two-phase RTD-CMOS pipelined circuits  [Article]

      Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)
      MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have ...