Now showing items 1-9 of 9

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      ASIC-in-the-loop methodology for verification of piecewise affine controllers  [Presentation]

      Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Castro, Javier; Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2012)
      This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. ...
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      Circuit implementation of piecewise-affine functions based on lattice representation  [Presentation]

      Martínez Rodríguez, Macarena Cristina; Baturone Castillo, María Iluminada; Brox Jiménez, Piedad (Institute of Electrical and Electronics Engineers, 2011)
      This paper introduces a digital architecture to implement piecewise-affine (PWA) functions based on representation methods from the lattice theory. Given an explicit and continuous PWA function, the parameters required to ...
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      Dedicated hardware IP module for extracting singular points from fingerprints  [Presentation]

      Martínez Rodríguez, Macarena Cristina; Arjona, Rosario; Brox Jiménez, Piedad; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2014)
      In this paper a new digital dedicated hardware IP module for extracting singular points from fingerprints is presented (in particular convex cores). This module comprises four main blocks that implement an image directional ...
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      Design methodology for FPGA implementation of lattice piecewise-affine functions  [Presentation]

      Martínez Rodríguez, Macarena Cristina; Baturone Castillo, María Iluminada; Brox Jiménez, Piedad (2011)
      This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions based on representation methods from the lattice theory. An off-line automatic processing starts at the algorithmic formulation ...
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      Design of trusted piecewise-affine controllers and virtual sensors into CMOS integrated circuits.  [Doctoral Thesis]

      Martínez Rodríguez, Macarena Cristina (2018-06-25)
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      Digital implementation of hierarchical piecewise-affine controllers  [Presentation]

      Baturone Castillo, María Iluminada; Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Gersnoviez, A.; Sánchez Solano, Santiago (Institute of Electrical and Electronics Engineers, 2011)
      This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the ...
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      Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach  [Article]

      Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2015)
      This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The ...
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      Reducing bit flipping problems in SRAM physical unclonable functions for chip identification  [Presentation]

      Eiroa, Susana; Castro, J.; Martínez Rodríguez, Macarena Cristina; Tena Sánchez, Erica; Brox Jiménez, Piedad; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2012)
      Physical Unclonable functions (PUFs) have appeared as a promising solution to provide security in hardware. SRAM PUFs offer the advantage, over other PUF constructions, of reusing resources (memories) that already exist ...
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      VLSI Design of Trusted Virtual Sensors  [Article]

      Martínez Rodríguez, Macarena Cristina; Prada Delgado, Miguel Ángel; Brox Jiménez, Piedad; Baturone Castillo, María Iluminada (Multidisciplinary Digital Publishing Institute, 2018)
      This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a ...