2017-01-182017-01-182000Acosta Jiménez, A.J., Jiménez, R.,...,Valencia Barrero, M. (2000). Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. En Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. (pp. 316-326). Berlin: Springer.978-3-540-41068-30302-9743http://hdl.handle.net/11441/52422This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two nbit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/bookPartinfo:eu-repo/semantics/openAccess10.1007/3-540-45373-3_33