Srivastava, MFerro, AlessandroSidun, ARosa Utrera, José Manuel de laODonoghue, KCantillon-Murphy, POHare, D2024-06-112024-06-112024Srivastava, M., Ferro, A., Sidun, A., Rosa Utrera, J.M.d.l., ODonoghue, K., Cantillon-Murphy, P. y OHare, D. (2024). A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing. IEEE Open Journal of Circuits and Systems, 5, 42-54. https://doi.org/10.1109/OJCAS.2024.3378653.2644-1225https://hdl.handle.net/11441/160329This work presents a small-area 2nd-order continuous-time ΔΣ Modulator (CT ΔΣM ) with a single low dropout regulator (LDO) serving as both the power supply for the CT ΔΣM and reference voltage buffer. The CT ΔΣM is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT ΔΣM consumes 300 μW of power when clocked at 10.24 MHz. The CT ΔΣM achieves a state-of-the-art area of 0.07 mm2.application/pdf13 p.engAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Analog-to-digital conversionContinuous-time delta-sigma modulationExcess loop-delay compensationFIR DACMagnetic sensorSensor interfaceinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1109/OJCAS.2024.3378653