Serrano Gotarredona, María TeresaLinares Barranco, BernabéVelarde Ramírez, Jesús2020-09-302020-09-302004Serrano Gotarredona, M.T., Linares Barranco, B. y Velarde Ramírez, J. (2004). A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion. En ISCAS 2004: IEEE International Symposium on Circuits and Systems (753-756), Vancouver, BC, Canada: IEEE Computer Society.0-7803-8251-Xhttps://hdl.handle.net/11441/101611A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region [1]. A mismatch characterization of NMOS and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able to predict current mismatch with a mean relative error of 13.5% in the weak inversion region and 5% in strong inversion. This is verified for 12 different curves, sweeping , and . Since data is available for 30 different sizes, the mismatch model can be expressed as function of transistor width W and L, independently. The proposed model, with explicit W and L dependency has been implemented in the Spectre simulator. Simulations reveal that such precise modeling of mismatch (with explicit W and L dependency) can improve analog circuit performance without penalty on power and area consumption: just by splitting transistors into the optimum number of segments.application/pdf4engAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1109/ISCAS.2004.1328304