2019-09-052019-09-052007Tortosa Navas, R., Aceituno, A., Rosa Utrera, J.M.d.l., Rodríguez Vázquez, Á.B. y Fernández Fernández, F.V. (2007). A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator. En Proceeding of the 2007 International Symposium on Circuits and Systems (ISCAS) (1-4), New Orleans, USA: Institute of Electrical and Electronics Engineers.1-4244-0921-7/07https://hdl.handle.net/11441/88984This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Continuous-Time CircuitsSigma-Delta Modulatorsinfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccess