Serrano Gotarredona, María TeresaLinares Barranco, Bernabé2020-10-212020-10-212012Serrano Gotarredona, M.T. y Linares Barranco, B. (2012). Design of adaptive nano/CMOS neural architectures. En ICECS 2012: 19th IEEE International Conference on Electronics, Circuits and Systems (949-952), Sevilla, España: IEEE Computer Society.978-1-4673-1261-5https://hdl.handle.net/11441/102098Memristive devices are a promising technology to implement dense learning synapse arrays emulating the high memory capacity and connectivity of biological brains. Recently, the implementation of STDP learning in memristive devices connected to spiking neurons have been demonstrated as well as the dependency of the form of the learning rule on the shape of the applied spike. In this paper, we propose a fully CMOS integrate-and-fire neuron generating a precisely shaped spike that can be tuned through programmable biases. The implementation of STDP learning is demonstrated through electrical simulations of a 4x4 array of memristors connected to 4 spiking neurons.application/pdf4engAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1109/ICECS.2012.6463504