Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

Ruiz de Clavijo Vázquez, PaulinoJuan Chico, JorgeBellido Díaz, Manuel JesúsMillán Calderón, AlejandroGuerrero Martos, David2017-01-192017-01-192002Ruiz de Clavijo Vázquez, P., Juan Chico, J.,...,Guerrero Martos, D. (2002). Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. En Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451 (pp. 400-408). Berlin: Springer.978-3-540-44143-40302-9743http://hdl.handle.net/11441/52479This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Levelinfo:eu-repo/semantics/bookPartinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1007/3-540-45716-X_40