Yousefzadeh, AmirrezaJablonski, M.Iakymchuk, T.Linares Barranco, AlejandroRosado, A.Plana, L.A.Serrano Gotarredona, María TeresaFurber, Steve B.Linares Barranco, Bernabé2020-02-142020-02-142017Yousefzadeh, A., Jablonski, M., Iakymchuk, T., Linares Barranco, A., Rosado, A., Plana, L.A.,...,Linares Barranco, B. (2017). Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems. En ISCAS 2017: IEEE International Symposium on Circuits and Systems Baltimore, MD, USA: IEEE Computer Society.978-1-4673-6853-72379-447Xhttps://hdl.handle.net/11441/93156Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging “neural spikes” among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bidirectional SATA connectors with a pair of LVDS (low voltage differential signaling) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links per LVDS physical connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs reaching a maximum event transmission speed of 75Meps (Mega Events per second) for 32-bit events at 3.0Gbps line data rate.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Neuromorphic SystemsVirtual WiringAddress event representation (AER)Scalable Neuromorphic Systemsinfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1109/ISCAS.2017.8050802