2018-07-312018-07-312010Suárez Cambre, M., Brea Sánchez, V.M., Domínguez Matas, C., Carmona Galán, R., Liñán Cembrano, G. y Rodríguez Vázquez, Á.B. (2010). Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology. En Latin American Symposium on Circuits ans Systems (1-4), Iguazu (Brasil): Institute of Electrical and Electronics Engineers.978-1-5090-2076-8https://hdl.handle.net/11441/77727This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.1mV in an area of approximately 220μm2 with a time response of less than 40ns and a static power dissipation of 1.125μW.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccess10.1109/LASCAS.2010.7410254