Fernández Pérez, José MaríaSánchez Fernández, Francisco J.Carmona Galán, Ricardo2018-03-222018-03-222007Fernández Pérez, J.M., Sánchez Fernández, F.J. y Carmona Galán, R. (2007). Performance evaluation and limitations of a vision system on a reconfigurable/programmable chip. Journal of Universal Computer Science, 13 (3), 440-453.0948-695X (impreso)0948-6968 (electrónico)https://hdl.handle.net/11441/71280This paper presents a survey of the characteristics of a vision system implemented in a reconfigurable/programmable chip (FPGA). System limitations and performance have been evaluated in order to derive specifications and constraints for further vision system synthesis. The system hereby reported has a conventional architecture. It consists in a central microprocessor (CPU) and the necessary peripheral elements for data acquisition, data storage and communications. It has been designed to stand alone, but a link to the programming and debugging tools running in a digital host (PC) is provided. In order to alleviate the computational load of the central microprocessor, we have designed a visual co-processor in charge of the low-level image processing tasks. It operates autonomously, commanded by the CPU, as another system peripheral. The complete system, without the sensor, has been implemented in a single reconfigurable chip as a SOPC. The incorporation of a dedicated visual co-processor, with specific circuitry for low-level image processing acceleration, enhances the system throughput outperforming conventional processing schemes. However, timemultiplexing of the dedicated hardware remains a limiting factor for the achievable peak computing power. We have quantified this effect and sketched possible solutions, like replication of the specific image processing hardware.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Image processingSystem-on-a-programmable-chip implementationAlgorithms implemented in hardware [Integrated Circuits]Hardware architecture [Computer Graphics]info:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccesshttps://doi.org/10.3217/jucs-013-03-0440