Castro López, RafaelFernández Fernández, Francisco VidalSantos Prieto, Fernando de los2025-10-232025-10-232025-06-09Santos Prieto, F.d.l. (2025). Optimization and Reliability Enhancement of Silicon PUFs Using Pairwise Element Comparisons. (Trabajo Fin de Máster Inédito). Universidad de Sevilla, Sevilla.https://hdl.handle.net/11441/178001Physical Unclonable Functions (PUFs) have emerged as a promising solution for ensuring security and data protection in low-cost, resource-constrained devices. By generating secure cryptographic keys on the fly, PUFs can outperform traditional approaches that rely on non-volatile memories (NVM), offering enhanced security without the need for permanent key storage. Their operation relies on the inherent variability of the manufacturing processes of devices and materials, leveraging the uniqueness and unpredictability introduced during fabrication. Importantly, a PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded due to several factors. For instance, traditional silicon PUFs, such as the SRAM and the Ring-Oscilaltor (RO) PUFs, are widely adopted but are known to suffer from reliability concerns that include susceptibility to temperature and supply voltage fluctuations, as well as long-term degradation due to circuit aging. Therefore, the need for more reliable PUFs in the face of these challenges is one of the driving forces behind ongoing innovation in silicon PUFs. On the other hand, silicon is not the only technology that could benefit from embedding reliable hardware security primitives within devices. Organic technologies are increasingly being adopted in applications that leverage their inherent flexibility and low fabrication costs. Most of these applications (such as sensors or wearables) can handle sensitive data acquired from the environment or the user, making security and data integrity essential requirements. PUFs developed using such technologies can provide a lightweight and efficient solution to ensure data protection and device-level security. However, integrating these security modules poses significant challenges, as additional reliability concerns emerge in the context of organic technologies. Several approaches, including pre-processing and post-processing methods, have been proposed to obtain a reliable PUF operation in the face of the reliability concerns mentioned above. For instance, regarding silicon PUFs, a new kind of aging-resilient devices the leverage charge trapping in the gate oxide of the transistors have been reported. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of other concerns, such as temperature variations. Similarly, as organic thin-film transistors (OTFTs) mature, the realization of PUFs using these devices is becoming increasingly feasible. However, further efforts are still required to fully understand their variability and to address the associated reliability challenges. The work presented here demonstrates that the reliability of both silicon-based and beyond-CMOS PUFs can be significantly improved. In particular, two novel techniques are proposed: (a) an optimization based algorithm applicable to any PUF that relies on pairwise comparisons; and (b) a temperature-aware parameter tuning method designed to compensate for temperature-induced unreliability in PUFs based on charge trapping.application/pdf71 p.engAttribution-NonCommercial-NoDerivatives 4.0 Internationalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/masterThesisinfo:eu-repo/semantics/openAccess