Millán Calderón, AlejandroJuan Chico, JorgeBellido Díaz, Manuel JesúsRuiz de Clavijo Vázquez, PaulinoGuerrero Martos, DavidOstúa Arangüena, Enrique2015-11-302015-11-302004Millán Calderón, A., Juan Chico, J., Bellido Díaz, M.J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D. y Ostúa Arangüena, E. (2004). Signal Sampling Based Transition Modeling for Digital Gates Characterization. Lecture Notes in Computer Science, 3254, 829-837.0302-9743http://hdl.handle.net/11441/31227Es una ponencia del Congreso: PATMOS 2004 : 14th International Workshop on Power and Timing Modeling, Optimization and Simulation. ISBN: 978-3-540-23095-3Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%.application/pdfenghttp://creativecommons.org/licenses/by-nc-nd/4.0/Digital circuitCMOSCharacterizationLogic simulationinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1007/978-3-540-30205-6_85