Medeiro Hidalgo, FernandoPérez Verdú, BelénRosa Utrera, José Manuel de laRodríguez Vázquez, Ángel Benito2018-07-242018-07-241997Medeiro Hidalgo, F., Pérez Verdú, B., Rosa Utrera, J.M.d.l. y Rodríguez Vázquez, Á.B. (1997). Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology. Journal Circuit Theory Applications, 25 (5), 319-334.0098-98861097-007Xhttps://hdl.handle.net/11441/77540This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16.4 bit at a digital output rate of 9.6 kHz with a power consumption of 1.7 mW. It yields a value of Power(W)/[2^resolution(bit) * Outpur rate(Hz)] which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Mixed-signal circuitsData conversionΣΔMOptimized designCAD toolsinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U