2020-01-242020-01-242005Tortosa Navas, R., Rosa Utrera, J.M.d.l., Rodríguez Vázquez, Á.B. y Fernández Fernández, F.V. (2005). Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study. En VLSI Circuits and Systems II (59-70), Sevilla, España: The International Society for Optical Engineering - SPIE.0277-786Xhttps://hdl.handle.net/11441/92293This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely, transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Analog-to-digital convertersContinuous-time circuitsSigma-delta modulatorsinfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccess10.1117/12.6079235516056