2020-01-162020-01-162019Viejo Cortés, J., Juan Chico, J., Bellido Díaz, M.J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D., Ostúa Arangüena, E. y Cano Quiveu, G. (2019). High-Performance Time Server Core for FPGA System-on-Chip. Electronics, 8 (5)2079-9292https://hdl.handle.net/11441/91716This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/System-on-chipDigital integrated circuitsField programmable gate array (FPGA)Network time synchronizationNetwork time protocolHardware timestampingInternet of Thingsinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccess10.3390/electronics8050528