Tena Sánchez, EricaAcosta Jiménez, Antonio José2025-01-232025-01-232019-02Tena Sánchez, E. y Acosta Jiménez, A.J. (2019). Logic Minimization and Wide Fan-In Issues in DPL-Based Cryptocircuits Against Power Analysis Attacks. International Journal of Circuit Theory and Applications, 47 (2), 238-253. https://doi.org/10.1002/cta.2587.0098-98861097-007Xhttps://hdl.handle.net/11441/167314This paper discusses the use of logic minimization techniques and wide fan-in primitives and how the design and evaluation of combinational blocks for full-custom dual-precharge-logic-based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate-level design of substitution boxes, widely used in block ciphers, using sense-amplifier–based logic in a 90-nm technology. The security of several proposals was evaluated with simulation-based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security-power-delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power-efficient.application/pdf16 p.engSide-channel attacksInformation securityLogic designOptimizationCryptographyFull-customDual precharge logic (DPL)info:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1002/cta.2587