Medeiro Hidalgo, FernandoDomínguez Castro, RafaelRodríguez Vázquez, Ángel BenitoHuertas Díaz, José Luis2020-03-122020-03-121992Medeiro Hidalgo, F., Domínguez Castro, R., Rodríguez Vázquez, Á.B. y Huertas Díaz, J.L. (1992). A prototype tool for optimum analog sizing using simulated annealing. En IEEE International Symposium on Circuits and Systems (1933-1936), San Diego, USA: Institute of Electrical and Electronics Engineers.0-7803-0593-00271-4310https://hdl.handle.net/11441/94147It is shown that using simulated annealing in combination with electrical simulation provides a powerful tool allowing unexperienced designer to size complex analogue building blocks starting from scratch. A cost function structure is proposed to map a set of specification targets into a combinatorial optimization problem which is in his turn solved by statistical methods. Applicability of the tool is demonstrated via several examples. In particular via the design of the building blocks for a 2μm CMOS 16bits 20 KHz second-order sigma-delta modulator.application/pdf4 p.engAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1109/ISCAS.1992.230431