Degradation Delay Model Extension to CMOS Gates

2017-01-192017-01-192000Juan Chico, J., Bellido Díaz, M.J.,...,Valencia Barrero, M. (2000). Degradation Delay Model Extension to CMOS Gates. En Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918 (pp. 149-158). Berlin: Springer.978-3-540-41068-30302-9743http://hdl.handle.net/11441/52449This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Degradation Delay Model Extension to CMOS Gatesinfo:eu-repo/semantics/bookPartinfo:eu-repo/semantics/openAccess10.1007/3-540-45373-3_15