2025-05-142025-05-142025Laguna, M., Marsal, E., Colodro Ruiz, F., Martínez Heredia, J.M. y Arahal, M.R. (2025). Time Interleaving in the Analogue Circuitry of Oversampled Digital-to-Analogue Converters: Proof of Concept. Electronics Letters, 61 (1), e70280. https://doi.org/10.1049/ell2.70280.1350-911X0013-5194https://hdl.handle.net/11441/172732This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.Digital-to-analog converters (DACs) based on sigma-delta modulation are implemented with analog components that have low accuracy requirements. As a result, they have been widely employed in high-frequency transmitter architectures over the past decades. Time interleaving techniques allow parallel structures to operate at reduced speeds, thereby mitigating speed limitations in digital circuits. However, a common approach involves multiplexing the outputs of these parallel structures to reconstruct a single digital signal, which is subsequently converted to an analog voltage using a high-speed, low-resolution DAC. This work investigates the feasibility of employing a parallel array of low-speed DACs instead. To compensate for mismatches in analog paths, a novel dynamic element matching technique is proposed. Experimental results demonstrate that the proposed approach exhibits the characteristics required for high-frequency transmitter applicationsapplication/pdf6 p.engAttribution-NonCommercial-NoDerivatives 4.0 Internationalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccess10.1049/ell2.70280