Juan Chico, JorgeViejo Cortés, JuliánBellido Díaz, Manuel Jesús2017-01-252017-01-252012Juan Chico, J., Viejo Cortés, J., y Bellido Díaz, M.J. (2012). Network Time Synchronization: A Full Hardware Approach. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606 (pp. 225-234). Berlin: Springer.978-3-642-36156-20302-9743http://hdl.handle.net/11441/52737Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system and software application. Each abstraction level greatly facilitates the design task at the cost of paying in performance and hardware resources usage. Network time synchronization is a good example of a complex system using several abstraction levels since the traditional solutions are a software application running on top of several software and hardware layers. In this contribution we study the case where a standards-compliant network time synchronization solution is fully implemented in hardware on a FPGA chip doing without any software layer. This solution makes it possible to implement very compact, inexpensive and accurate synchronization systems to be used either stand-alone or as embedded cores. Some general aspects of the design experience are commented together with some figures of merit. As a conclusion, full hardware implementations of complex digital systems should be seen as a feasible design option, from which great performance advantages can be expected, provided that we can find a suitable set of tools and control the design development costs.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/digital systemshardwarenetwork time synchronizationFPGAinfo:eu-repo/semantics/bookPartinfo:eu-repo/semantics/openAccesshttps://doi.org/10.1007/978-3-642-36157-9_23