2025-01-302025-01-302024-08-052169-3536https://hdl.handle.net/11441/167892In this paper, we present hardware implementations of the lightweight TinyJAMBU cipher with reduced power consumption using a mechanism based on shift register parallelization. The power consumption in digital circuits depends linearly on the switching activity of the logic gates. The parallelization technique reduces the number of switches per clock cycle of the shift registers, which can significantly reduce power consumption. This technique has been applied to the TinyJAMBU cipher, a f inalist in the NIST lightweight cryptography standardization process with the lowest resource and power consumption. The implementations we present use the logical parallelization technique in the cipher’s NLFSR, which is the basic block of TinyJAMBU, and in the key register. Simulation results are presented to demonstrate the effectiveness of the proposed technique in reducing power consumption, achieving a reduction of more than 30% in dynamic power consumption compared to the standard implementation, with almost no increase in resource consumption. Therefore, the ciphers proposed in this paper are highly suitable for use in applications with severe constraints on available resources and power.application/pdf8engAttribution-NonCommercial-NoDerivatives 4.0 Internationalhttp://creativecommons.org/licenses/by-nc-nd/4.0/AEADLightweightCryptographyNISTTinyJAMBUinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccess10.1109/ACCESS.2024.3438378