2019-10-102019-10-102000Río Fernández, R.d., Medeiro Hidalgo, F., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (2000). Reliable analysis of settling errors in SC integrators-application to the design of high-speed /spl Sigma//spl Delta/ modulators. En 2000 IEEE International Symposium on Circuits and Systems (ISCAS) (IV-417-IV-420), Ginebra, Suiza: Institute of Electrical and Electronics Engineers.0-7803-5482-6https://hdl.handle.net/11441/89604This paper presents a detailed study on the transient response of SC integrators which takes into account the effects of amplifier finite gain-bandwidth product, slew-rate, and parasitic capacitances. Unlike previous models, both the integration and the sampling phases are considered. Experimental measurements of the settling error power of a 2nd-order /spl Sigma//spl Delta/ modulator are used to validate the model. When compared to previous models, the new one provides more reliable estimations of the defective settling in optimized high-speed /spl Sigma//spl Delta/ modulators. The results in the paper show up to -16 dB difference in the estimation of the in-band error power of a 2-1-1 mb /spl Sigma//spl Delta/M intended for 14 bit@4 M Samples/s.application/pdfengAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccess10.1109/ISCAS.2000.8587775402122