On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter

2023-05-312023-05-312020Feitoza, R.S., Barragan, M.J., Ginés Arteaga, A.J. y Mir, S. (2020). On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter. En European Test Symposium (9131588-), Tallín, Estonia: Institute of Electrical and Electronics Engineers (IEEE).978-172814312-51530-1877https://hdl.handle.net/11441/146829This paper describes a BIST technique for the static linearity test of Vcm-based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the Vcm-based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.application/pdf2 p.engAtribución 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc/4.0/On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converterinfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccess10.1109/ETS48528.2020.9131588