Presentation
Analog neural networks for real-time constrained optimization
Author/s | Domínguez Castro, Rafael
Rodríguez Vázquez, Ángel Benito Huertas Díaz, José Luis Sánchez Sinencio, Edgar Linares Barranco, Bernabé |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 1990 |
Deposit Date | 2020-03-18 |
Published in |
|
ISBN/ISSN | 0271-4310 |
Abstract | Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI techniques are explored. Discrete-time analog techniques are considered due to their inherent accuracy, ... Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI techniques are explored. Discrete-time analog techniques are considered due to their inherent accuracy, programmability, and reconfigurability. A general architecture for minimizing piecewise functions by using gradient schemes is introduced. Switched-capacitor (SC) building blocks featuring improved characteristics in terms of area occupation and operation speed are presented. The implementation of the architectures by using the newest switched-current techniques is discussed. The layout of a 3-μm CMOS SC prototype for a quadratic optimization problem with linear constraints is given. |
Citation | Domínguez Castro, R., Rodríguez Vázquez, Á.B., Huertas Díaz, J.L., Sánchez Sinencio, E. y Linares Barranco, B. (1990). Analog neural networks for real-time constrained optimization. En IEEE International Symposium on Circuits and Systems (1867-1870), Nueva Orleans, USA: Institute of Electrical and Electronics Engineers. |
Files | Size | Format | View | Description |
---|---|---|---|---|
Analog Neural Networks for ... | 529.5Kb | [PDF] | View/ | |