A processing element architecture for high-density focal plane analog programmable array processors

Liñán Cembrano, Gustavo; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael; Rodríguez Vázquez, Ángel Benito

doi:10.1109/ISCAS.2002.1010230

Ponencia

dc.creator	Liñán Cembrano, Gustavo	es
dc.creator	Espejo Meana, Servando Carlos	es
dc.creator	Domínguez Castro, Rafael	es
dc.creator	Rodríguez Vázquez, Ángel Benito	es
dc.date.accessioned	2020-01-30T15:37:41Z
dc.date.available	2020-01-30T15:37:41Z
dc.date.issued	2002
dc.identifier.citation	Liñán Cembrano, G., Espejo Meana, S.C., Domínguez Castro, R. y Rodríguez Vázquez, Á.B. (2002). A processing element architecture for high-density focal plane analog programmable array processors. En International Symposium on Circuits and Systems (ISCAS) (III-341-III-344), Phoenix-Scottsdale, USA: Institute of Electrical and Electronics Engineers.
dc.identifier.isbn	0-7803-7448-7	es
dc.identifier.issn	0271-4310	es
dc.identifier.uri	https://hdl.handle.net/11441/92599
dc.description.abstract	The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 × 3 convolution masks. The vision chip has been implemented in a standard 0.35μm CMOS technology. The main PE related figures are: 180 cells/mm2, 18 MOPS/cell, and 180 μW/cell.	es
dc.description.sponsorship	Office of Naval Research (USA) N68171-98-C-9004	es
dc.description.sponsorship	Euopean Union IST-1999-19007	es
dc.description.sponsorship	Comisión Interministerial de Ciencia y Tecnología TIC1 999-0826	es
dc.format	application/pdf	es
dc.language.iso	eng	es
dc.publisher	Institute of Electrical and Electronics Engineers	es
dc.relation.ispartof	International Symposium on Circuits and Systems (ISCAS) (2002), p III-341-III-344
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.title	A processing element architecture for high-density focal plane analog programmable array processors	es
dc.type	info:eu-repo/semantics/conferenceObject	es
dcterms.identifier	https://ror.org/03yxnpp24
dc.type.version	info:eu-repo/semantics/acceptedVersion	es
dc.rights.accessRights	info:eu-repo/semantics/openAccess	es
dc.contributor.affiliation	Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo	es
dc.relation.projectID	N68171-98-C-9004	es
dc.relation.projectID	IST-1999-19007	es
dc.relation.projectID	TIC1 999-0826	es
dc.relation.publisherversion	https://doi.org/10.1109/ISCAS.2002.1010230	es
dc.identifier.doi	10.1109/ISCAS.2002.1010230	es
idus.format.extent	4 p.	es
dc.publication.initialPage	III-341	es
dc.publication.endPage	III-344	es
dc.eventtitle	International Symposium on Circuits and Systems (ISCAS)	es
dc.eventinstitution	Phoenix-Scottsdale, USA	es

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