dc.creator | Linares Barranco, Alejandro | es |
dc.creator | Paz Vicente, Rafael | es |
dc.creator | Gómez Rodríguez, Francisco de Asís | es |
dc.creator | Jiménez Fernández, Ángel Francisco | es |
dc.creator | Rivas Pérez, Manuel | es |
dc.creator | Jiménez Moreno, Gabriel | es |
dc.creator | Civit Balcells, Antón | es |
dc.date.accessioned | 2019-12-18T10:28:21Z | |
dc.date.available | 2019-12-18T10:28:21Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | Linares Barranco, A., Paz Vicente, R., Gómez Rodríguez, F.d.A., Jiménez Fernández, Á.F., Rivas Pérez, M., Jiménez Moreno, G. y Civit Balcells, A. (2010). On the AER Convolution Processors for FPGA. En ISCAS 2010: IEEE International Symposium on Circuits and Systems (4237-4240), Paris, France: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-4244-5308-5 | es |
dc.identifier.issn | 0271-4302 | es |
dc.identifier.uri | https://hdl.handle.net/11441/91064 | |
dc.description.abstract | Image convolution operations in digital computer
systems are usually very expensive operations in terms of
resource consumption (processor resources and processing time)
for an efficient Real-Time application. In these scenarios the
visual information is divided into frames and each one has to be
completely processed before the next frame arrives in order to
warranty the real-time. A spike-based philosophy for computing
convolutions based on the neuro-inspired Address-Event-
Representation (AER) is achieving high performances. In this
paper we present two FPGA implementations of AER-based
convolution processors for relatively small Xilinx FPGAs
(Spartan-II 200 and Spartan-3 400), which process 64x64 images
with 11x11 convolution kernels. The maximum equivalent
operation rate that can be reached is 163.51 MOPS for 11x11
kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock.
Formulations, hardware architecture, operation examples and
performance comparison with frame-based convolution
processors are presented and discussed. | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2006-11730-C03-02 | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2009-10639-C04-02 | es |
dc.description.sponsorship | Junta de Andalucía P06-TIC-01417 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | ISCAS 2010: IEEE International Symposium on Circuits and Systems (2010), p 4237-4240 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | On the AER Convolution Processors for FPGA | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | TEC2006-11730-C03-02 | es |
dc.relation.projectID | TEC2009-10639-C04-02 | es |
dc.relation.projectID | P06-TIC-01417 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/5537577 | es |
dc.identifier.doi | 10.1109/ISCAS.2010.5537577 | es |
dc.contributor.group | Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación | es |
idus.format.extent | 4 | es |
dc.publication.initialPage | 4237 | es |
dc.publication.endPage | 4240 | es |
dc.eventtitle | ISCAS 2010: IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Paris, France | es |
dc.relation.publicationplace | New York, USA | es |