Presentation
LVDS Serial AER Link performance
Author/s | Miró Amarante, María Lourdes
Jiménez Fernández, Ángel Francisco Linares Barranco, Alejandro Gómez Rodríguez, Francisco de Asís Paz Vicente, Rafael Jiménez Moreno, Gabriel Civit Balcells, Antón Serrano Gotarredona, Rafael |
Department | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Publication Date | 2007 |
Deposit Date | 2019-07-09 |
Published in |
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ISBN/ISSN | 1-4244-0920-9 0271-4302 |
Abstract | Address-Event-Representation (AER) is a
communication protocol for transferring asynchronous events
between VLSI chips, originally developed for bio-inspired
processing systems (for example, image processing). Such
systems ... Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows analysing a LVDS Serial AER link produced by a Spartan 3 FPGA, or by a commercial LVDS transceiver. The interface allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps. |
Project ID. | IST-2001-34124 (CAVIAR)
TIC-2003-08164-C03- 02 |
Citation | Miró Amarante, M.L., Jiménez Fernández, Á.F., Linares Barranco, A., Gómez Rodríguez, F.d.A., Paz Vicente, R., Jiménez Moreno, G.,...,Serrano Gotarredona, R. (2007). LVDS Serial AER Link performance. En ISCAS 2007: IEEE International Symposium on Circuits and Systems (1537-1540), New Orleans, USA: IEEE Computer Society. |
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LVDS Serial AER Link.pdf | 452.1Kb | [PDF] | View/ | |