Ponencia
Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters
Autor/es | Ruiz Amaya, Jesús
Rosa Utrera, José Manuel de la Delgado Restituto, Manuel |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2004 |
Fecha de depósito | 2018-11-12 |
Publicado en |
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Resumen | This paper presents a toolbox for the
time-domain simulation and optimization-based
high-level synthesis of pipeline analog-to-digital converters
in MATLAB®. Behavioral models of building blocks,
including their critical ... This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of pipeline analog-to-digital converters in MATLAB®. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK® as C-compiled S-functions. This approach significantly speeds up system- level simulations while keeping high accuracy − verified with HSPICE − and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s ADC for a PLC chipset is designed to show the capabilities of the presented tool. |
Agencias financiadoras | European Union (UE) |
Cita | Ruiz Amaya, J., Rosa Utrera, J.M.d.l. y Delgado Restituto, M. (2004). Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters. En Conference on Design of Circuits and Integrated Systems, Bordeaux (Francia). |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Simulation-based.pdf | 585.6Kb | [PDF] | Ver/ | |