dc.creator | Parra Fernández, María del Pilar | es |
dc.creator | Acosta Jiménez, Antonio José | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2017-10-04T10:34:43Z | |
dc.date.available | 2017-10-04T10:34:43Z | |
dc.date.issued | 2002 | |
dc.identifier.citation | Parra Fernández, M.d.P., Acosta, A. y Valencia Barrero, M. (2002). Selective Clock-Gating for Low Power/Low Noise Synchronous Counters. En PATMOS 2002 : 12th International Workshop on Power and Timing Modeling, Optimization and Simulation (448-457), Sevilla, España: Springer. | |
dc.identifier.isbn | 978-3-540-44143-4 | es |
dc.identifier.issn | 0302-9743 | es |
dc.identifier.uri | http://hdl.handle.net/11441/64996 | |
dc.description.abstract | The objective of this paper is to explore the applicability of clock
gating techniques to binary counters in order to reduce the power consumption
as well as the switching noise generation. A measurement methodology
to establish right comparisons between different implementations of gateclocked
counters is presented. Basically two ways of applying clock gating
are considered: clock gating on independent bits and clock gating on groups
of bits. The right selection of bits where clock gating must be applied and the
suited composition of groups of bits is essential when applying this technique.
We have found groupment of bits is the best option when applying
clock gating to reduce power consumption and specially to reduce noise generation. | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TIC2000-1350 | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TIC2001- 2283 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Springer | es |
dc.relation.ispartof | PATMOS 2002 : 12th International Workshop on Power and Timing Modeling, Optimization and Simulation (2002), p 448-457 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Selective Clock-Gating for Low Power/Low Noise Synchronous Counters | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TIC2000-1350 | es |
dc.relation.projectID | TIC2001- 2283 | es |
dc.relation.publisherversion | https://link.springer.com/chapter/10.1007/3-540-45716-X_45 | es |
dc.identifier.doi | 10.1007/3-540-45716-X_45 | es |
idus.format.extent | 10 | es |
dc.publication.initialPage | 448 | es |
dc.publication.endPage | 457 | es |
dc.eventtitle | PATMOS 2002 : 12th International Workshop on Power and Timing Modeling, Optimization and Simulation | es |
dc.eventinstitution | Sevilla, España | es |
dc.relation.publicationplace | Berlin | es |
dc.contributor.funder | Ministerio de Ciencia y Tecnología (MCYT). España | |