dc.creator | Baena Oliva, María del Carmen | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2017-01-19T12:16:49Z | |
dc.date.available | 2017-01-19T12:16:49Z | |
dc.date.issued | 2002 | |
dc.identifier.citation | Baena Oliva, M.d.C., Juan Chico, J.,...,Valencia Barrero, M. (2002). Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. En Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451 (pp. 353-362). Berlin: Springer. | |
dc.identifier.isbn | 978-3-540-44143-4 | es |
dc.identifier.issn | 0302-9743 | es |
dc.identifier.uri | http://hdl.handle.net/11441/52483 | |
dc.description.abstract | Accurate estimation of switching activity is very important in
digital circuits. In this paper we present a comparison between the evaluation
of the switching activity calculated using logic (Verilog) and electrical
(HSPICE) simulators. We also study how the variation on the delay model
(min, typ, max) and parasitic effects affect the number of transitions in the
circuit. Results show a variable and significant overestimation of this
measurement using logic simulators even when including postlayout effects.
Furthermore, we show the contribution of glitches to the overall switching
activity, giving that the treatment of glitches in conventional logic simulators
is the main cause of switching activity overestimation. | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TIC 2000-1350 | |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TIC 2002-2283 | |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Springer | es |
dc.relation.ispartof | Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451 | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level | es |
dc.type | info:eu-repo/semantics/bookPart | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TIC 2000-1350 | es |
dc.relation.projectID | TIC 2002-2283 | es |
dc.relation.publisherversion | http://link.springer.com/chapter/10.1007%2F3-540-45716-X_35 | es |
dc.identifier.doi | 10.1007/3-540-45716-X_35 | es |
idus.format.extent | 10 | es |
dc.publication.initialPage | 353 | es |
dc.publication.endPage | 362 | es |
dc.relation.publicationplace | Berlin | es |
dc.contributor.funder | Ministerio de Ciencia y Tecnología (MCYT). España | |