Capítulo de Libro
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
Autor/es | Baena Oliva, María del Carmen
Juan Chico, Jorge Bellido Díaz, Manuel Jesús Ruiz de Clavijo Vázquez, Paulino Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2002 |
Fecha de depósito | 2017-01-19 |
Publicado en |
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ISBN/ISSN | 978-3-540-44143-4 0302-9743 |
Resumen | Accurate estimation of switching activity is very important in
digital circuits. In this paper we present a comparison between the evaluation
of the switching activity calculated using logic (Verilog) and electrical
(HSPICE) ... Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) simulators. We also study how the variation on the delay model (min, typ, max) and parasitic effects affect the number of transitions in the circuit. Results show a variable and significant overestimation of this measurement using logic simulators even when including postlayout effects. Furthermore, we show the contribution of glitches to the overall switching activity, giving that the treatment of glitches in conventional logic simulators is the main cause of switching activity overestimation. |
Agencias financiadoras | Ministerio de Ciencia y Tecnología (MCYT). España |
Identificador del proyecto | TIC 2000-1350
TIC 2002-2283 |
Cita | Baena Oliva, M.d.C., Juan Chico, J.,...,Valencia Barrero, M. (2002). Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. En Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451 (pp. 353-362). Berlin: Springer. |
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