dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Parra Fernández, María del Pilar | es |
dc.creator | Baena Oliva, María del Carmen | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.creator | Potestad Ordóñez, Francisco Eugenio | es |
dc.date.accessioned | 2022-01-26T11:44:44Z | |
dc.date.available | 2022-01-26T11:44:44Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Jiménez Fernández, C.J., Parra Fernández, M.d.P., Baena Oliva, M.d.C., Valencia Barrero, M. y Potestad Ordoñez, F.E. (2018). FPGA design example for maximum operating frequency measurements. En TAEE 2018: XIII Technologies Applied to Electronics Teaching Conference La Laguna, Tenerife: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-5386-0928-6 | es |
dc.identifier.uri | https://hdl.handle.net/11441/129273 | |
dc.description.abstract | The best way to learn how to design digital systems
at the RT level is to use practical examples. In addition, from a
teaching point of view, the more practical they are, the more
attractive to students. But for a design to be attractive, even if it
is presented with a low complexity, it is not possible to do it in a
single practice session. This paper presents, as a demonstrator,
the design at RT level and its implementation in FPGA of a
digital system that uses the Trivium flow cipher and on which
measurements of maximum operating frequency are made. This
circuit is designed in three laboratory sessions of about two hours
each. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2013-45523-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2016-80549-R | es |
dc.description.sponsorship | Consejo Superio de Investigaciones Científicas (CSIC) LACRE CSIC 201550E039 | es |
dc.format | application/pdf | es |
dc.format.extent | 5 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | TAEE 2018: XIII Technologies Applied to Electronics Teaching Conference (2018). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | VHDL | es |
dc.subject | Digital system design | es |
dc.subject | Field Programmable Gate Array (FPGA) | es |
dc.subject | Chipscope | es |
dc.title | FPGA design example for maximum operating frequency measurements | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC2013-45523-R | es |
dc.relation.projectID | TEC2016-80549-R | es |
dc.relation.projectID | LACRE CSIC 201550E039 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8476046 | es |
dc.identifier.doi | 10.1109/TAEE.2018.8476046 | es |
dc.eventtitle | TAEE 2018: XIII Technologies Applied to Electronics Teaching Conference | es |
dc.eventinstitution | La Laguna, Tenerife | es |
dc.relation.publicationplace | New York, USA | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |
dc.contributor.funder | Consejo Superior de Investigaciones Científicas (CSIC) | es |