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Ponencia
Modeling of Real Bistables in VHDL
(IEEE Computer Society, 1993)
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two ...
Ponencia
Redes e interconexiones de procesadores con capacidad de tolerancia a fallos
(Universidad Politécnica de Madrid, 1992)
Se describe una familia de redes de interconexión para sistemas multiprocesadores. Estas redes utilizan buses múltiples estructurados en varios niveles e incorporan el concepto de tolerancia a fallos mediante redundancia ...
Ponencia
New CMOS VLSI Linear Self-Timed Architectures
(1995)
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve some problems encountered in synchronous VLSI circuits. However; a main difference between ...