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Ponencia
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
(IEEE Computer Society, 2001)
As delay models used in logic timing simulation become more and more complex, the problem of model parameter values extraction arise as an important issue, which is necessary to face in order to achieve a practical i ...
Ponencia
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial ...
Ponencia
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
Capítulo de Libro
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
(Springer, 2002)
Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) ...
Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...