Now showing items 1-10 of 27
Modeling of Real Bistables in VHDL
(IEEE Computer Society, 1993)
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two ...
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...
Chapter of Book
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) ...
New CMOS VLSI Linear Self-Timed Architectures
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve some problems encountered in synchronous VLSI circuits. However; a main difference between ...
Low Power Implementation of Trivium Stream Cipher
This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The de-sign was simulated with Modelsim, and synthesized with Synopsys in three CMOS ...
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to ...
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an ...
Formación de profesores noveles en tecnología electrónica: una primera aproximación
(Universidad de Sevilla, Instituto de Ciencias de la Educación, 2005)
Los profesores universitarios de áreas científicas y técnicas están cada vez más preocupados por desarrollar adecuadamente sus tareas docentes. Una muestra de este hecho se presenta en este trabajo en el que se describe ...
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial ...