Browsing Ponencias (Tecnología Electrónica) by Subject "High speed CMOS design"
Now showing items 1-2 of 2
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Presentation
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
(Society of Photo-Optical Instrumentation Engineers (SPIE), 2005)Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay ...
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Presentation
Automatic logic synthesis for parallel alternating latches clocking schemes
(SPIE Digital Library, 2007)This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called ...