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Mostrando ítems 1-10 de 38
Ponencia
Current-mode building blocks for CMOS-VLSI design of chaotic neural networks
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJTs. ...
Ponencia
Integer-based digital processor for the estimation of phase synchronization between neural signals
(Institute of Electrical and Electronics Engineers, 2016)
This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by ...
Ponencia
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
(Institute of Electrical and Electronics Engineers, 1993)
This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits ...
Ponencia
Self-calibration of neural recording sensors
(Institute of Electrical and Electronics Engineers, 2014)
This paper reports a calibration system for automatically adjusting the bandpass and gain characteristics of programmable E×G sensors. The calibration mechanism of the bandpass characteristic is based on a mixed-signal ...
Ponencia
Real-time phase correlation based integrated system for seizure detection
(The Society of Photo-Optical Instrumentation Engineers, 2017)
This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying ...
Ponencia
A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter
(The International Society for Optical Engineering- SPIE, 2005)
This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. ...
Ponencia
Discrete-time integrated circuits for chaotic communication
(Institute of Electrical and Electronics Engineers, 1997)
This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital filter structures with overflow non-linearity. Simulation results from an integrated prototype using ...
Ponencia
Transformer based front-end for a low power 2.4 GHz transceiver
(Institute of Electrical and Electronics Engineers, 2010)
A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer to convert the 100 Ω antenna impedance to almost 1 kΩ and so facilitates a low power transmitter and ...
Ponencia
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends for neural recording applications. These techniques are employed for handling Common-Mode (CM) ...
Ponencia
Experimental verification of chaotic encryption of audio using monolithic chaotic modulators
(SPIE- The International Society for Optical Engineering, 1995)
This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. It is based on a g m-C modulator/demodulator analog CMOS IC that implements a 3rd-order nonlinear ...