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Mostrando ítems 1-10 de 43
Artículo
Efficient state reduction methods for PLA-based sequential circuits
(Institute of Electrical and Electronics Engineers, 1992)
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are ...
Artículo
Using Building Blocks to Design Analog Neuro-Fuzzy Controllers
(Institute of Electrical and Electronics Engineers, 1995)
We present a parallel architecture for fuzzy controllers and a methodology for their realization as analog CMOS chips for low- and medium-precision applications. These chips can be made to learn through the adaptation of ...
Artículo
On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's
(Institute of Electrical and Electronics Engineers, 1990)
A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., ...
Artículo
Design considerations for integrated continuous-time chaotic oscillators
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant ...
Artículo
Switched-Current Chaotic Neurons
(Institution of Engineering and Technology, 1994)
The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6µm CMOS technology. The neuron soma ...
Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
Artículo
Analog Neural Programmable Optimizers in CMOS VLSI Technologies
(Institute of Electrical and Electronics Engineers, 1992)
A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind ...
Artículo
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of ...
Artículo
A real-time clustering microchip neural engine
(Institute of Electrical and Electronics Engineers, 1996)
This paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm, but has been modified resulting in a more VLSI-friendly ...
Artículo
Multiplexing architecture for mixed-signal CMOS fuzzy controllers
(Institute of Electrical and Electronics Engineers, 1998)
Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the ...