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Mostrando ítems 511-520 de 592
Ponencia
An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band ...
Ponencia
A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization
(The International Society for Optical Engineering - SPIE, 2005)
This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator ...
Ponencia
Comparison of matroid intersection algorithms for large circuit analysis
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the generation of the symbolic expressions. Both techniques are examined from the point of view of matroid ...
Ponencia
In vivo measurements with a 64-channel extracellular neural recording integrated circuit
(Institute of Electrical and Electronics Engineers, 2014)
This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific Integrated Circuit (ASIC) developed at IMSE and gives details of the computer interface used for real-time ...
Ponencia
A 2.2 μW analog front-end for multichannel neural recording
(Institute of Electrical and Electronics Engineers, 2017)
In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain ...
Artículo
Tunable Low Noise Amplifier Implementation With Low Distortion Pseudo-Resistance for in Vivo Brain Activity Measurement
(Institute of Electrical and Electronics Engineers, 2014)
This paper presents a low power neural signal amplifier with tunable cut-off frequencies. The presented compact amplifier, which is used for sensing various types of neural signals, reduces the size and the power consumption ...
Ponencia
Behavioral modeling of PWL analog circuits using symbolic analysis
(Institute of Electrical and Electronics Engineers, 1998)
Behavioral models are used both for top-down design and for bottom-up verification. During top-down design, models are created that reflect the nominal behavior of the different analog functions, as well as the constraints ...
Artículo
CMOS 2.4μm chaotic oscillator: Experimental verification of chaotic encryption of audio
(Institution of Engineering and Technology, 1996)
The Letter reports the first experimental verification of chaotic encryption of audio using custom monolithic chaotic oscillators. We use Gm-C techniques to realise a chaotic modulator/ demodulator IC that implements a ...
Ponencia
Tactile on-chip pre-processing with techniques from artificial retinas
(The International Society for Optical Engineering - SPIE, 2005)
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide ...
Artículo
Macromodelling for analog design and robustness boosting in bio-inspired computing models
(Society of Photo-Optical Instrumentation Engineers, 2005)
Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads ...