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Mostrando ítems 461-470 de 597
Artículo
VLSI Design of Trusted Virtual Sensors
(Multidisciplinary Digital Publishing Institute, 2018)
This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a ...
Ponencia
Dedicated Hardware IP Module for Fingerprint Recognition
(IEEE, 2015-08-06)
This work presents a dedicated hardware IP module for fingerprints recognition based on a feature, named QFingerMap, which is very suitable for VLSI design. FPGA implementation results of the IP module are given. A ...
Artículo
FLIP-Q: A QCIF resolution focal-plane array for low-power image processing
(Institute of Electrical and Electronics Engineers, 2011)
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified ...
Ponencia
A Sub-μVRms Chopper Front-End for ECoG Recording
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path ...
Artículo
Methodology to improve the model of series inductance in CMOS integrated inductors
(Slovak Technical University, 2018)
This paper presents a systematic optimization methodology to achieve an accurate estimation of series inductance of inductors implemented in standard CMOS technologies. Proposed method is based on an optimization procedure ...
Ponencia
A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications
(Institute of Electrical and Electronics Engineers, 2016)
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption ...
Artículo
Switched-capacitor neural networks for linear programming
(Institution of Engineering and Technology, 1988)
A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques and is thus suitable for monolithic implementation. The connection of the proposed circuit to analogue ...
Ponencia
In-pixel ADC for a vision architecture on CMOS-3D technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a ...
Ponencia
Practical considerations for the design of cascade multi-bit high-frequency /spl Sigma//spl Delta/ modulators
(Institute of Electrical and Electronics Engineers, 1998)
Recommendations are given for efficient design of high-frequency /spl Sigma//spl Delta/ modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design ...
Ponencia
CMOS current-mode chaotic neurons
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. ...