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Mostrando ítems 51-60 de 61
Ponencia
Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK
(The International Society for Optical Engineering - SPIE, 2005)
This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded ...
Ponencia
An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band ...
Ponencia
In vivo measurements with a 64-channel extracellular neural recording integrated circuit
(Institute of Electrical and Electronics Engineers, 2014)
This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific Integrated Circuit (ASIC) developed at IMSE and gives details of the computer interface used for real-time ...
Ponencia
A 2.2 μW analog front-end for multichannel neural recording
(Institute of Electrical and Electronics Engineers, 2017)
In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain ...
Artículo
CMOS 2.4μm chaotic oscillator: Experimental verification of chaotic encryption of audio
(Institution of Engineering and Technology, 1996)
The Letter reports the first experimental verification of chaotic encryption of audio using custom monolithic chaotic oscillators. We use Gm-C techniques to realise a chaotic modulator/ demodulator IC that implements a ...
Ponencia
Electrical-level synthesis of pipeline ADCs
(Institute of Electrical and Electronics Engineers, 2008)
This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., ...
Ponencia
A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation
(Institute of Electrical and Electronics Engineers, 2017)
A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise ...
Ponencia
Integrated circuit blocks for a DCSK chaos radio
(Institute of Electrical and Electronics Engineers, 1998)
A proposal for an integrated digital communication system using a DCSK chaotic modulation scheme is presented. It is a point-to-point wireless system capable of supporting half-duplex real-time voice and low data rate ...
Artículo
Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective ...
Ponencia
A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline communication receiver. As an additional attribute, the filter provides programmable boost in the pass-band ...