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Ponencia
A Direct Synthesis Method of Cascaded Continuous-Time Sigma-Delta Modulators
(2005)
This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time ...
Artículo
Artículo
Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+
(Institute of Electrical and Electronics Engineers, 2004)
We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) ...
Ponencia
An Alternative DfT Methodology to Test High-Resolution ΣΔ Modulators
(Institute of Electrical and Electronics Engineers, 2004)
In this paper, a novel DfT methodology to test high-resolution ΣΔ Modulators (ΣΔM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of ...
Ponencia
High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology
(Institute of Electrical and Electronics Engineers, 2001)
We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable ...
Ponencia
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator
(Institute of Electrical and Electronics Engineers, 2006)
This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using ...
Ponencia
Using CAD Tools for the Automatic Design of Low-Power ΣΔ Modulators
(1997)
This paper illustrates the use of a CAD methodology to design a high-resolution 2nd-order ZA modulator with optimized power con- sumption.The fabricated prototype in 0.7um CMOS technology features 16.4-bit resolution at ...
Capítulo de Libro
Tools for Automated Design of ΣΔ Modulators
(Springer, 1997)
We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these ...
Ponencia
A 2.5-V CMOS Wideband Sigma-Delta Modulator
(Institute of Electrical and Electronics Engineers, 2003)
A high-performance Sigma-Delta modulator for wireline communication applications is presenfed It employs a 4th-order cascade multi-bit architecfure that requires only 16 oversampling ratio, and has been implemented using ...
Ponencia
Analysis of Clock Jitter Error in Multibit Continuous-Time ΣΔ modulators with NRZ Feedback Waveform
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a detailed study of the clock jitter error in multibit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Closed-form expressions are derived for the in-band error power and the ...