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Mostrando ítems 21-30 de 52
Ponencia
Application of piecewise-linear switched-capacitor circuits for random number generation
(Institute of Electrical and Electronics Engineers, 1989)
An unconventional application of switched-capacitor (SC) circuits is discussed. A systematic method for the design of piecewise-linear (PL) parasitic-insensitive SC chaotic discrete maps is given. A simple circuit which ...
Ponencia
CNN universal chip in CMOS technology
(Institute of Electrical and Electronics Engineers, 1994)
This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of an array of 32×32 completely programmable CNN cells. Input image can be loaded in optical or electrical ...
Artículo
CMOS optical-sensor array with high output current levels and automatic signal-range centring
(Institution of Engineering and Technology, 1994)
A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range centring according to illumination conditions are presented. The high output current levels allow the ...
Ponencia
Implementation of non-linear templates using a decomposition technique by a 0.5 /spl mu/m CMOS CNN universal chip
(Institute of Electrical and Electronics Engineers, 2000)
This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new prototype, called CNNUC3, follows the cellular neural network universal machine computing paradigm. ...
Ponencia
Mismatch-induced tradeoffs and scalability of mixed-signal vision chips
(Institute of Electrical and Electronics Engineers, 2002)
This paper explores different trade-offs associated with the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing ...
Artículo
A switched-capacitor broadband noise generator for CMOS VLSI
(Institution of Engineering and Technology, 1991)
A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the implementation of a very simple chaotic discrete-time system. The concept is demonstrated via a 3ftm CMOS ...
Artículo
Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
(Institute of Electrical and Electronics Engineers, 1993)
This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are ...
Ponencia
CNN technology in action
(Institute of Electrical and Electronics Engineers, 2000)
Two Cellular Neural Net Universal Machine (CNN-UM) prototypes are demonstrated in action. The first one is the latest 4096 cell-processor, analog I/O, analogic CNN visual microprocessor, on which online video image processing ...
Ponencia
Realization of non-linear templates using the CNNUC3 prototype
(Institute of Electrical and Electronics Engineers, 2000)
Demonstrates the processing capabilities of an analog programmable array processor chipMINUS/CNNUC3-which follows the cellular neural network Universal Machine computing paradigm. Due to its very advanced features and ...
Ponencia
Switched-current techniques for image processing Cellular Neural Networks in MOS VLSI
(Institute of Electrical and Electronics Engineers, 1992)
An architecture and related building blocks are presented for the realization of image processing tasks using current-mode analog-digital circuits. The architecture is based on the Cellular Neural Network paradigm while ...