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Ponencia
A complete retargeting methodology for mixed-signal IC designs
(Institute of Electrical and Electronics Engineers, 2001)
In this paper, an efficient methodology to retargeting and reuse of embedded mixed-signal blocks is presented. Parametrized layout templates, accurate behavioral modeling of mixed-signal blocks, and appropriate mechanisms ...
Ponencia
Mixed-signal map-configurable integrated chaos generator for digital communication systems
(2001)
In this paper, the methodological aspects for the design of mixed-signal map-configurable chaos generators are presented. Such techniques have been applied in the integration, embedded in a complete FM-DCSK modem, of a ...
Ponencia
Analysis and Experimental Characterization of Idle Tones in 2nd-Order Bandpass Sigma-Delta Modulators - A 0.8μm CMOS Switched-Current Case Study
(Institute of Electrical and Electronics Engineers, 2001)
Ths paper analyses the tonal behaviour of the quantization noise in 2nd-order bandpass SD modulators. The analysis previously performed for lowpass modulators is extended to the bandpass case. As a result, closed-form ...
Ponencia
Effect of Non-Linear Settling Error on The Harmonic Distortion of Fully-Differential Switched-Current BandPass Sigma-Delta Modulators
(Institute of Electrical and Electronics Engineers, 2001)
This paper presents a detailed study of the effect of the non-linear settling on the harmonic distortion of BandPass SD Modulators (BP-ΣΔMs) realized using Fully Differential (FD) SwItched-current (SI) circuits. Based on ...
Ponencia
Analysis and Modeling of the Non-Linear Sampling Process in Switched-Current Circuits - Application to Bandpass Sigma-Delta Modulators
(2001)
This paper presents a precise model for the transient behaviour of Fully Differential (FD) SwItched-current (SI) memory cells placed at the front-end of high-speed A/D interfaces. This model allows us to analyze the main ...
Ponencia
High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology
(Institute of Electrical and Electronics Engineers, 2001)
We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable ...
Ponencia
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
(European Conference on Circuit Theory and Design, 2001)
This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M ...
Ponencia
A behavioral modeling concept and practice of CNN-UM VLSI implementations
(Institute of Electrical and Electronics Engineers, 2001)
In this paper we introduce a novel simulation time bounded behavioral modeling technique that optimally selects the incorporated block models. The method has been specially developed for fast performance evaluation of large ...
Ponencia
Study of Non-Linear S/H Operation in Switched-Current Circuits Using Volterra Series - Application to BandPass Sigma-Delta Modulators
(2001)
This paper analyses the transient behaviour of SwItched-current (SI) memory cells placed at the front-end of high-speed A/D interfaces. Based on the Volterra series method, the non-linear sampling process occurring in ...
Ponencia
Top-Down Design of a xDSL 14-bit 4MSh ZA Modulator in Digital CMOS Technology
(Institute of Electrical and Electronics Engineers, 2001)
This paper describes the design of a Sigma-Delta modulator aimed for A/D conversion in xDSL applications, featuring 14-bit@4Msample/s in a 0.35μm mainstream digital CMOS technology. Architecture selection, modulator sizing ...